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R2J20601NP
Driver - MOS FET Integrated SiP (DrMOS)
REJ03G0237-0200 Rev.2.00 Oct 12, 2004
Description
The R2J20601NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose. Integrating a driver and both high-side and low-side power MOS FETs, the new device is also compliant with the package standard "Driver - MOS FET integrated SiP (DrMOS)" proposed by Intel Corporation.
Features
* * * * * * * * * * * Built-in power MOS FET suitable for applications with 12 V input and low output voltage Built-in driver circuit which matches the power MOS FET Built-in tri-state input function which can support a number of PWM controllers Operating-voltage range: 7.9 V to 16 V High-frequency operation (above 1 MHz) possible Large average output current (35 A) Achieve low power dissipation (About 5.6 W at 1 MHz, 25 A) Controllable driver: Remote on/off Built-in Schottky diode for bootstrapping Low-side drive voltage can be independently set Small package: QFN56 (8 mm x 8 mm x 0.8 mm)
Outline
VCIN BOOT GH VIN 56 Reg5V Driver Tab High-side MOS Tab 1 14 15
DISBL#
MOS FET Driver
VSWH Low-side MOS Tab
PWM 43 CGND VLDRV GL PGND 42
28 29 (Bottom view) QFN56 package 8 mm x 8 mm
Rev.2.00, Oct 12, 2004, page 1 of 13
R2J20601NP
Block Diagram
VCIN Reg5V BOOT GH Driver chip
UVL DISBL# 2 A CGND 5 V Gen.
SBD VIN High-side MOS FET Level shifter
VSWH VCIN
PWM
Input logic (TTL level) (3 state in)
Overlap protection Low-side MOS FET
PGND
CGND
VLDRV
GL
Notes: 1. Truth table for the DISBL# pin.
DISBL# Input "L" "Open" "H" Driver Chip Status Shutdown (GL, GH = "L") Shutdown (GL, GH = "L") Enable (GL, GH = "Active")
2. Output signal from the UVL block
"H" UVL Output Logic Level "L" VL VH VCIN For activation For shutdown
Rev.2.00, Oct 12, 2004, page 2 of 13
R2J20601NP
Pin Arrangement
VLDRV
3
CGND
14
13
12
11
10
9
8
7
6
5
4
2
VIN VIN VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND PGND PGND
CGND
1 56 55
BOOT
VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
GH
NC
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PWM DISBL# Reg5V NC GL CGND VSWH VSWH VSWH VSWH VSWH VSWH VSWH VSWH
VIN
CGND
54 53 52 51 50 49 48
VSWH
47 46 45 44 43
VSWH
VSWH
(Top view)
Pin Description
Pin Name CGND NC VLDRV VCIN BOOT GH VIN VSWH PGND GL Reg5V DISBL# PWM Pin No. 1, 6, 51, Tab 2, 53 3 4 5 7 8 to 20, Tab 21, 40 to 50, Tab 22 to 39 52 54 55 56 Description Control signal ground No connect Low side gate supply voltage Control input voltage (+12 V input) Bootstrap voltage pin High side gate signal Input voltage Phase output/Switch output Power ground Low side gate signal +5 V logic power supply output Signal disable PWM drive logic input Pin for Monitor Disabled when DISBL# is "L" Remarks Should be connected to PGND externally For 5 V to 12 V gate drive voltage for Low side gate driver Driver Vcc input To be supplied +5 V through internal SBD Pin for Monitor
Rev.2.00, Oct 12, 2004, page 3 of 13
VSWH
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
R2J20601NP
Absolute Maximum Ratings
(Ta = 25C)
Item Power dissipation Average output current Input voltage Supply voltage Low side driver voltage Switch node voltage BOOT voltage DISBL# voltage PWM voltage Reg5V current Operating junction temperature Storage temperature Symbol Pt(25) Pt(110) Iout VIN VCIN VLDRV VSWH VBOOT Vdisble Vpwm Ireg5V Tj-opr Tstg Rating 25 8 35 -0.3 to 16 -0.3 to 16 -0.3 to 16 -0.3 to 16 -0.3 to 22 -0.3 to VCIN -0.3 to (Reg5V + 0.3) -10 to 0.1 -40 to 150 -55 to 150 Units W W A V V V V V V V mA C C Note 1 1 2 2 2 2 2 2 2 3
Notes: 1. Pt(25) represents a PCB temperature of 25C, and Pt(100) represents 100C. 2. Rated voltages are relative to voltages on the CGND and PGND pins. 3. For rated current, (+) indicates inflow to the chip and (-) indicates outflow.
Safe Operating Area 40 35
Average Output Current (A)
30 25 20 15 10 5 0 0 25 50 75 100 125 150 175
PCB Temperature (C)
Rev.2.00, Oct 12, 2004, page 4 of 13
R2J20601NP
Electrical Characteristics
(Ta = 25C, VCIN = 12 V, VLDRV = 5 V, VSWH = 0 V, unless otherwise specified)
Supply Item VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN bias current VLDRV bias current PWM Input PWM rising threshold PWM falling threshold PWM input resistance Tri-state shutdown window 5V Regulator DISBL# Input Note: Shutdown hold-off time Output voltage Line regulation Load regulation Disable threshold Enable threshold Symbol VH VL dUVL ICIN ILDRV VH-PWM VL-PWM RIN-PWM VIN-SD tHOLD-OFF Vreg Vreg-line Vreg-load VDISBL VENBL Min 8.1 6.5 -- 10.5 31.5 3.5 0.9 30 VL-PWM -- 4.75 -10 -10 0.9 1.9 Typ 9.0 7.2 1 1.8 * 14.0 40.7 3.8 1.2 50 -- 240 * 5.0 0 0 1.2 2.4
1
Max 9.9 7.9 -- 18.5 46.5 4.1 1.5 70 VH-PWM -- 5.25 10 10 1.5 2.9 5.0
Units V V V mA mA V V k V ns V mV mV V V A
Test Conditions
VH - VL fPWM = 1 MHz, ton-PWM = 125 ns fPWM = 1 MHz, ton-PWM = 125 ns
PWM = 1 V
VCIN = 12 V to 16 V Ireg = 0 to 10 mA
Input current IDISBL 0.5 2.0 1. Reference values for design. Not 100% tested in production.
DISBL# = 1 V
Rev.2.00, Oct 12, 2004, page 5 of 13
R2J20601NP
Typical Application
+12 V +5 V to 12 V +12 V
VCIN VLDRV BOOT DISBL# VIN
Reg5V
DrMOS
VSWH
PWM CGND GH
PGND GL
VCIN VLDRV BOOT DISBL# VIN
Reg5V
DrMOS
VSWH
PWM PWM1 CGND GH
PGND GL
PWM PWM2 control circuit PWM3
PWM4 VCIN VLDRV BOOT DISBL# VIN
+1.3 V
Reg5V
DrMOS
VSWH
Signal Power GND GND
PWM CGND GH
PGND GL
VCIN VLDRV BOOT DISBL# VIN
Reg5V
DrMOS
VSWH
PWM CGND GH
PGND GL
Rev.2.00, Oct 12, 2004, page 6 of 13
R2J20601NP
Test Circuit
VB VLDRV VCIN
A A A
IIN ILDRV ICIN
V VIN
VCIN VLDRV BOOT DISBL# VIN
Reg5V
DrMOS
VSWH
5 V pulse
PWM CGND GH
PGND GL
Electric load
IO
Averaging Average Output Voltage V VO circuit
Note: PIN = IIN x VIN + ILDRV x VLDRV + ICIN x VCIN POUT = IO x VO Efficiency = POUT / PIN PLOSS(DrMOS) = PIN - POUT
Rev.2.00, Oct 12, 2004, page 7 of 13
R2J20601NP
Typical Data
Power Loss vs. Output Current 9
VIN = 12 V VLDRV = 5 V
Power Loss vs. Input Voltage 10
VCIN = 12 V VLDRV = 5 V 9 VOUT = 1.3 V fpwm = 1 MHz L = 0.45 H
8 VCIN = 12 V
Power Loss (W)
7 VOUT = 1.3 V 6 L = 0.45 H 5 4 3 2
Power Loss (W)
fpwm = 1 MHz
8 7 6 5
1 0 0 5 10 15 20 25 30 4 5 6 7 8
Iout = 25 A Iout = 30 A
9 10 11 12 13 14 15 16
Output Current (A)
Input Voltage Vin (V)
Power Loss vs. Output Voltage 10 9
Power Loss (W)
Power Loss vs. Switching Frequency 11
VIN = 12 V VLDRV = 5 V VOUT = 1.3 V
10 VCIN = 12 V
Power Loss (W)
Iout = 25 A Iout = 30 A
9 L = 0.45 H 8 7 6 5
8
VIN = 12 V VCIN = 12 V 7 VLDRV = 5 V fpwm = 1 MHz L = 0.45 H
6 5
4 3 250 500 750 1000
4 0.8
Iout = 25 A Iout = 30 A
1.2
1.6
2.0
2.4
2.8
3.2
3.6
1250
1500
Output Voltage Vout (V)
Switching Frequency (kHz)
Rev.2.00, Oct 12, 2004, page 8 of 13
R2J20601NP
Typical Data (cont.)
Power Loss vs. Output Inductance 10 9
Power Loss (W)
Power Loss vs. VLDRV 10
VIN = 12 V VCIN = 12 V 9 VOUT = 1.3 V fpwm = 1 MHz L = 0.45 H
8
Power Loss (W)
Iout = 25 A Iout = 30 A
VIN = 12 V VCIN = 12 V 7 VLDRV = 5 V VOUT = 1.3 V fpwm = 1 MHz
8 7 6 5 4
Iout = 25 A Iout = 30 A
6 5 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (H)
5
6
7
8
9 10 11 12 13 14 15 16 VLDRV (V)
Average ILDRV vs. Switching Frequency 200
VIN = 12 V VCIN = 12 V VOUT = 1.3 V 160 IOUT = 0 L = 0.45 H
Average ICIN vs. Switching Frequency 25
VIN = 12 V VCIN = 12 V VOUT = 1.3 V 20 IOUT = 0 L = 0.45 H
Average ILDRV (mA)
120
Average ICIN (mA)
VLDRV = 5 V VLDRV = 12 V VLDRV = 16 V
15
80
10
40
5
0 250
500
750
1000
1250
1500
0 250
VLDRV = 5 V VLDRV = 12 V VLDRV = 16 V
500
750
1000
1250
1500
Switching Frequency (kHz)
Switching Frequency (kHz)
Rev.2.00, Oct 12, 2004, page 9 of 13
R2J20601NP
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. Driver The driver has two types of power-supply voltage input pin, VCIN and VLDRV. VCIN supplies the operating voltage to the internal logic circuit. The low-side driving voltage is applied to VLDRV, so setting of the gate-driving voltage for the low-side MOS FET is independent of the voltage on VCIN. The VLDRV setting voltage is from 5 V to 16 V. The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the driver is disabled as long as VCIN is 9 V or less. On cancellation of UVL, the driver remains enabled until the UVL input is driven to 7.2 V or less. The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit , the built-in 5 V regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and the 5 V regulator is not disabled.
VCIN L H H H VLDRV >5 V >5 V >5 V >5 V DISBL# L H Open Reg5V 0 5V 5V 5V Driver state Disable (GL, GH = L) Disable (GL, GH = L) Active Disable (GL, GH = L)
Voltages from -0.3 V to VCIN can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a resistor, etc., to pull the DISBL# line up to VCIN are both possible. The built-in 5 V regulator is a series regulator with temperature compensation. The voltage output by this regulator determines the operating voltage of the internal logic and gate-voltage swing for the high-side MOS FET. A ceramic capacitor with a value of 0.1 F or more must be connected between the CGND plane and the Reg5V pin. The PWM pin is the signal input pin for the driver chip. The input-voltage range is -0.3 V to (Reg5V + 3 V). When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low.
PWM L H GH L H GL H L
Rev.2.00, Oct 12, 2004, page 10 of 13
R2J20601NP The PWM input is TTL level and has hysteresis. When the PWM input signal is abnormal, e.g., when the signal route from the control IC is abnormal, the tri-state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3.8 V or more is required to make the circuit return to normal operation.
240 ns(tHOLD-OFF) 240 ns(tHOLD-OFF)
PWM
3.8 V 1.2 V
GH
GL
240 ns(tHOLD-OFF)
240 ns(tHOLD-OFF)
PWM
3.8 V 1.2 V
GH
GL
Figure 1
Rev.2.00, Oct 12, 2004, page 11 of 13
R2J20601NP The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal operation; after the PWM input signal has stayed in the hysteresis window for 240 ns (typ.) and the tri-state detection signal has been driven high, the transistor M1 is turned off. From this circuit configuration, we can see that the voltage on the PWM pin when open-circuit will be about 2.5 V, so the tri-state protection function will operate.
Reg5V M1 50 k PWM pin Input logic 50 k To internal control Tri-state detection signal
Figure 2 Equivalent Circuit for the PWM-pin Input For the high-side driver, the BOOT pin is the power-supply voltage pin and voltage VSWH provides a standard for operation of the high-side driving circuit. Consequently, the difference between the voltage on the BOOT and VSWH pins becomes the gate swing for the high-side MOS FET. Connect a bootstrap capacitor between the BOOT pin and the VSWH pin. Since the Schottky barrier diode (SBD) is connected between the BOOT and Reg5V pins, this bootstrap capacitor is charged up to 5 V. When the high-side MOS FET is turned on, voltage VSWH becomes equal to VIN, so VBOOT is boosted to VSWH + 5 V. The GH and GL pins are the gate-monitor pins for each MOS FET. MOS FETs The MOS FETs incorporated in R2J20601NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
Rev.2.00, Oct 12, 2004, page 12 of 13
R2J20601NP
Package Dimensions
Unit: mm
8.00 0.10 42 43 29
AB 28
8.00 0.10
28
43
C0.40
0.15 C
56 1
0.15 C
15
0.40 0.10
15 14 0.50
14
56 1 0.23 0.05
0.10 M C A B
// 0.10 C 0.08 C
0 - 0.05 0.20
0.80 Max
C
Package Code JEDEC JEITA Mass (reference value)
TNP-56TV -- -- 0.2 g
Rev.2.00, Oct 12, 2004, page 13 of 13
0.85 2.25 0.55
3.50
0.85
0.85 29
3.55
0.55 2.20 0.85 42
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